Kaushik Chandra Deva Sarma
Kaushik Chandra Deva Sarma Assistant Professor Department of Instrumentation Engineering ()
QUALIFICATIONS PhD(Tezpur University),M.Tech(Tezpur University)
AREA OF INTERESTS

Semiconductor Devices, Power Electronics, Optoelectronics, Sensors

CONTACT: Phone: 9706490533 Email: kcd.sarma@cit.ac.in
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PUBLICATIONS:

 

List of Publications (Selected)

Journal Publications

[1]     K C D Sarma, D Deka " An Approach for Potential Modelling of Symmetric Double Gate Junctionless Transistor with Multi Material Gate", International Journal of Applied Engineering Research (IJAER) (Accepted).

[2]      K C D Sarma " A Physics Based Approach for Threshold Voltage Modelling of Symmetric Double Gate  Junctionless Transistor With Multi Material Gate ", Journal of Nanoelectronics and Optoelectronics,       American Scientific Publishers, Vol. 13, No.4, pages 479-483, 2018

[3]    K C D Sarma and S. Sharma, "An Analytical Approach for Drain Current Modelling of A Symmetric Double Gate Junctionless Transistor", Journal of Nanoelectronics and Optoelectronics, American Scientific Publishers, Vol. 13, No.9, pages 1332-1339, 2018

[4]     K C D Sarma and S. Sharma, "Carrier Mobility Enhancement of Symmetric Double Gate  Junctionless Transistor”, Journal of Nanoelectronics and Optoelectronics, American Scientific Publishers, Vol.12, No.10, 2017

[5]    K C D Sarma and S. Sharma, "An Approach for Complete 2-D Analytical Potential Modelling of Fully Depleted Symmetric Double Gate Junction Less Transistor", Journal of Computational Electronics, Springer, Vol. 14, No. 3, pages 717-725, 2015

[6]    K C D Sarma and S. Sharma, "Scale Length Determination of Gate All Around (Regular Hexagonal Cross Section) Junctionless Transistor",  International Journal of Applied Engineering Research (IJAER) , Vol. 10, No. 2, pages 4751-4762, 2015

[7]      K C D Sarma, A Mallik, A Bhatnagar "Microcontroller Based Optical power meter for Lab Applications", Journal of Instrument Society of India, Vol. 40, June,2010.

Conference Publications

[1]     K C D Sarma and S. Sharma, "Scale Length Determination of Gate All Around (Regular Pentagonal Cross Section) Fully Depleted Junctionless Transistor", In IEEE  International Conference on Advances in Engineering and Technology Research (ICAETR), Dr. Virendra Swarup Group of Institutions,  Unnao, UP, pages 1-5, 1-2 August,2014

[2]    K C D Sarma and S. Sharma, "Scale Length Determination of Gate All Around (Octagonal Cross Section) Junctionless Transistor", In International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV), NIT, Meghalaya, pages 1-5,  29-30th January ,2015

[3]       K C D Sarma and S. Sharma, "A Method for Determination of Depletion Width of Single and Double Gate Junction Less Transistor", In International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV), NIT, Meghalaya,  pages 114-119, 29-30th January ,2015

[4]    K C D Sarma, S. Sharma and C. Hazarika, "Scale Length Determination of a Fully Depleted Surrounding Gate (Rectangular Cross Section) Junction Less Transistor", In International Conference on Electrical, Electronics, Signals, Communication & Optimization-EESCO, pages 1-4, 24-25 Jan-2015,Visakhapatnam,  Andhra Pradesh, India

[5]    K C D Sarma "A Study on The Effect of Source-Drain Length on Device Performane of Junctionless Transistor", In 580th International Conference on Innovative Engineering Technologies (ICIET), 1-2 April, Dubai, UAE

 

Book Chapter

[1]    Sarma, K. C. D. and Sharma, S. A Review on Evolution of MOSFET with Special Emphasis on Junctionless Transistor, In Ajay Kumar, B. S. and Sarkar, D., editors, Advanced Engineering Research and Applications, ISBN:978-93-84443-48-1, Research India Publications.

 

 

COURSE ENGAGEMENT:
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